With the spread of mobile communication through mobile phones, services have recently been provided based on a wireless communication system with high-speed capability, e.g., W-CDMA or CDMA-2000 technology. Direct sequence spread spectrum is used in such a mobile communication system to improve a communication rate and a call quality. A pseudo noise (PN) code, which is pseudo-random binary data, is used as a spreading code for the direct sequence spread spectrum. A PN code generator having a small circuit scale and high-speed capability is desired.
FIG. 14 is a circuit diagram illustrating a conventional PN code generator 80, and FIG. 15 is a diagram depicting an operation of the conventional PN code generator 80.
As illustrated in FIG. 14, the conventional PN code generator 80 is configured of a shift register consisting of fifteen registers FF1 through FF15 connected in series, and a single exclusive-OR gate XR. A feedback output of the last stage register FF15 is input through the exclusive-OR gate XR to the first stage register FF1. An output of the first stage register FF1 is input to the exclusive-OR gate XR.
Referring to FIG. 15, suppose that the initial contents of the individual registers FF1 through FF15 are D1 through D15, respectively. If a clock pulse is applied to each of the registers FF1 through FF15, the contents thereof are shifted by one bit into the next register FF and, further, the contents of the first stage register FF1 becomes contents obtained as a result of the exclusive-OR operation of the contents of the first stage register FF1 itself and the contents of the last stage register FF15. This is performed in response to the application of each clock pulse.
There is proposed a circuit for generating parallel pseudo-random data (Japanese Laid-open Patent Publication Nos. 9-321585 and 2002-342072).
In the case of the PN code generator 80 as illustrated in FIG. 14, one-bit data is produced every clock cycle. Accordingly, time corresponding to two clock cycles is necessary to produce two-bit data, and likewise, time corresponding to “n” clock cycles is necessary to produce n-bit data.
In order to produce n-bit data, e.g., 8-bit data, at high speed, it is necessary to appropriately increase the clock rate, which unfortunately makes the circuit configuration complicated.
The devices disclosed in Japanese Laid-open Patent Publication Nos. 9-321585 and 2002-342072 are capable of outputting multi-bit data in parallel; however the circuit configuration thereof is complex.